1. Field of the Invention
The present invention relates to manufacturing small dimension features of objects, such as integrated circuits, using photolithographic masks. More particularly, the present invention relates to the application of phase shift masking to complex layouts for integrated circuits and similar objects.
2. Description of Related Art
Phase shift masking has been applied to create small dimension features in integrated circuits. Typically the features have been limited to selected elements of the design, which have a small, critical dimension. See, for example, U.S. Pat. No. 5,766,806.
Although manufacturing of small dimension features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more extensively in the manufacturing of such devices. However, the extension of phase shift masking to more complex designs results in a large increase in the complexity of the mask layout problem. For example, when laying out phase shift windows on dense designs, phase conflicts will occur. One type of phase conflict is a location in the layout at which two phase shift windows having the same phase are laid out in proximity to a feature to be exposed by the masks, such as by overlapping of the phase shift windows intended for implementation of adjacent lines in the exposure pattern. If the phase shift windows have the same phase, then they do not result in the optical interference necessary to create the desired feature. Thus, it is necessary to prevent inadvertent layout of phase shift windows in phase conflict near features to be formed in the layer defined by the mask.
In the design of a single integrated circuit, millions of features may be laid out. The burden on data processing resources for iterative operations over such large numbers of features can be huge, and in some cases makes the iterative operation impractical. The layout of phase shift windows and the assignment phase shift values to such windows, for circuits in which a significant amount of the layout is accomplished by phase shifting, is one such iterative operation which has been impractical using prior art techniques.
Another problem that is associated with the use of phase shift masking arises from the need for two different mask patterns for implementation of a layer of material having small dimension features. Existing systems expose the wafer using a binary mask pattern using a stepper having optical settings optimized for the binary mask pattern, and expose the wafer using the phase shift mask pattern using a stepper having optical settings optimized for the phase shift mask pattern. Typically, the optical settings are quite different. For example, a phase shift pattern is usually exposed using a highly coherent radiation source. However, binary masks achieve better results having less coherent radiation sources. Thus, between the two exposures, the wafer is required to sit while the settings and masks are changed within the stepper. During the time the wafer sits, the quality of the resist can degrade. Furthermore, the time involved in moving the wafer and adjusting a stepper slow down the manufacturing process. For background concerning optical lithography and the phase shift masking, see Wong, RESOLUTION ENHANCEMENT TECHNIQUES IN OPTICAL LITHOGRAPHY, SPIE Press, Bellingham, Wash. (2001).
It is useful to understand the common stepper settings and parameters used in so called “gate shrink” phase shifting designs. A “gate shrink” design, or mask, is simply a layout, or mask, where significant portions of a pattern, usually field polysilicon, must still print properly using the corresponding binary trim mask, while portions such as transistor gates are formed using phase shifting, resulting in so-called “shrunk” gates.
Generally, phase shifting masks require a low partial coherence a arrangement in the stepper, so that the light exposing the wafer is highly coherent.
In contrast, when working with a binary pattern on a mask that has densely packed and small features, high partial coherence σ stepper settings producing less coherent light, and/or off-axis-illumination (OAI), or other illumination configurations are employed.
For that reason, the binary trim pattern on a mask for a gate shrink-type design would commonly be exposed using low coherency (high σ) or off-axis illumination. But, the phase shifting pattern on a mask for such a gate shrink-type design would use high coherency (low σ) illumination. This requires an adjustment of the projection system in the stepper, typically a change in size of an aperture, between the phase shifting pattern and trim pattern exposures.
Because of these and other complexities, implementation of a phase shift masking technology for complex designs will require improvements in the approach to the design of phase shift masks.